Power-Aware Computer Systems : 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers / edited by Babak Falsafi, T. N. VijayKumar.

Springer eBooks

Microarchitecture- and Circuit-Level Techniques -- An Optimized Front-End Physical Register File with Banking and Writeback Filtering -- Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization -- Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors -- Low-Overhead Core Swapping for Thermal Management -- Power-Aware Memory and Interconnect Systems -- Software–Hardware Cooperative Power Management for Main Memory -- Energy-Aware Data Prefetching for General-Purpose Programs -- Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems -- Context-Independent Codes for Off-Chip Interconnects -- Frequency-/Voltage-Scaling Techniques -- Dynamic Processor Throttling for Power Efficient Computations -- Effective Dynamic Voltage Scaling Through CPU-Boundedness Detection -- Safe Overprovisioning: Using Power Limits to Increase Aggregate Throughput -- Power Consumption Breakdown on a Modern Laptop -- Erratum -- Erratum.

This book contributes the thoroughly refereed post-proceedings of the 4th International Workshop on Power-Aware Computer Systems, PACS 2004, held in Portland, OR, USA in December 2004. The 12 revised full papers presented were carefully reviewed, selected, and revised for inclusion in the book. The papers span a wide spectrum of topics in power-aware systems; they are organized in topical sections on microarchitecture- and circuit-level techniques, power-aware memory and interconnect systems, and frequency- and voltage-scaling techniques.

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