Advanced hardware design for error correcting codes / edited by Cyrille Chavet, Philippe Coussy.
Tipo de material:
TextoEditor: Cham : Springer International Publishing : Springer, 2015Descripción: ix, 192 páginas : 81 ilustraciones, 25 ilustraciones en colorTipo de contenido: - texto
- computadora
- recurso en línea
- 9783319105697
- TK7888.4
Contenidos:
User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey. .
No hay ítems correspondientes a este registro
Springer eBooks
User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey. .
Para consulta fuera de la UANL se requiere clave de acceso remoto.