CMOS PLL Synthesizers: Analysis and Design / by Keliu Shu, Edgar Sánchez-Sinencio.

Por:

Shu, Keliu [autor]

Colaborador(es):

Tipo de material: Texto

TextoSeries The International Series in Engineering and Computer Science, Analog Circuits and Signal Processing ; 783Editor: Boston, MA : Springer US, 2005Descripción: XVI, 215 páginas, recurso en líneaTipo de contenido:

texto

Tipo de medio:

computadora

Tipo de portador:

recurso en línea

ISBN:

9780387236698

Formatos físicos adicionales: Edición impresa:: Sin títuloClasificación LoC:

TK1-9971

Recursos en línea:

Conectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)

Contenidos:

Frequency Synthesizer for Wireless Applications -- PLL Frequency Synthesizer -- ?? Fractional-N PLL Synthesizer -- Enhanced Phase Switching Prescaler -- Loop Filter with Capacitance Multiplier -- Other Building Blocks of PLL -- Prototype Measurement Results -- Conclusions.

Resumen: CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.

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Springer eBooks

CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.

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