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| 001 | 205907 | ||
| 003 | MX-SnUAN | ||
| 005 | 20160429151259.0 | ||
| 008 | 120404s2007 njua g 001 0 eng d | ||
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_aMX-SnUAN _bspa _cMX-SnUAN _erda |
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_aTK7885.7 _b.V34 2007 |
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_aVahid, Frank _eautor _9222309 |
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| 245 | 1 | 0 |
_aVerilog for digital design / _cFrank Vahid, Roman Lysecky. |
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_aHoboken, N. J. : _bJohn Wiley & Sons, _cc2007. |
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| 300 |
_axvi, 173 páginas : _bilustraciones ; _c24 cm. |
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_atexto _btxt _2rdacontent |
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_ano mediado _bn _2rdamedia |
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_avolumen _bnc _2rdacarrier |
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| 500 | _aIncluye índice | ||
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_aVHDL (Lenguaje de descripción de hardware) _9222310 |
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_aLysecky, Roman, _eautor _9222311 |
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