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008			150903s2006 xxu| o |||| 0|eng d
020			_a9780387364957 _99780387364957
024	7		_a10.1007/0387364951 _2doi
035			_avtls000331292
039		9	_a201509030720 _bVLOAD _c201404120622 _dVLOAD _c201404090402 _dVLOAD _c201401311409 _dstaff _y201401301206 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aSutherland, Stuart. _eautor _9300457
245	1	0	_aSystemVerilog for Design : _bA Guide to Using SystemVerilog for Hardware Design and Modeling / _cby Stuart Sutherland, Simon Davidmann, Peter Flake.
250			_aSecond Edition.
264		1	_aBoston, MA : _bSpringer US, _c2006.
300			_axxx, 418 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_ato SystemVerilog -- SystemVerilog Declaration Spaces -- SystemVerilog Literal Values and Built-in Data Types -- SystemVerilog User-Defined and Enumerated Types -- SystemVerilog Arrays, Structures and Unions -- SystemVerilog Procedural Blocks, Tasks and Functions -- SystemVerilog Procedural Statements -- Modeling Finite State Machines with SystemVerilog -- SystemVerilog Design Hierarchy -- SystemVerilog Interfaces -- A Complete Design Modeled with SystemVerilog -- Behavioral and Transaction Level Modeling.
520			_aSystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs. These important extensions enable the representation of complex digital logic in concise, accurate, and reusable hardware models. All key SystemVerilog design features are presented, such as declaration spaces, two-state data types, enumerated types, user-defined types, structures, unions, interfaces, and RTL coding extensions. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. Design engineers, engineering managers and engineering students working with all sizes and types of digital designs, whether FPGA, ASIC or full custom, will find this book to be an invaluable learning tool and reference guide. The second edition of this book reflects the official IEEE 1800-2005 SystemVerilog standard. This IEEE SystemVerilog standard adds new capabilities, clarifications, and changes to the Accellera 3.1 SystemVerilog upon which the first edition of this book was based. Significant updates and revisions in the new edition include: A new chapter showing how to use SystemVerilog packages with single-file and multi-file compilers. - New code examples illustrating correct usage of the IEEE version of SystemVerilog. - Updated coding guidelines reflecting the capabilities of current simulator and synthesis Electronic Design Automation tools such as digital simulators and synthesis compilers. "SystemVerilog makes it easier to produce more efficient and concise descriptions of complex hardware designs. The authors of this book have been involved with the development of the language from the beginning, and who is better to learn from than those involved from day one?" — Greg Spirakis, Vice President of Design Technology Intel Corporation "Sun has been a driving force in SystemVerilog from its inception. SystemVerilog can significantly improve the productivity of designers in the coming years, and this book is a comprehensive reference text for engineers who want to learn about SystemVerilog for their next generation designs." — Sunil Joshi, Vice President of Software Technologies & Compute Resources Sun Microsystems, Inc. "SystemVerilog addresses the need for efficient and powerful modeling essential to support the complexity, size and scale of next generation hardware designs. This book explains how to use SystemVerilog effectively and provides numerous examples to illustrate how each of the language constructs can best be utilized." — Chris Malachowsky, Co-Founder and Vice President of Hardware NVIDIA Corp.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aDavidmann, Simon. _eautor _9300458
700	1		_aFlake, Peter. _eautor _9300459
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387333991
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/0-387-36495-1 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c277573 _d277573