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008 150903s2006 xxu| o |||| 0|eng d
020 _a9780387334035
_99780387334035
024 7 _a10.1007/0387334033
_2doi
035 _avtls000331058
039 9 _a201509030727
_bVLOAD
_c201404120603
_dVLOAD
_c201404090343
_dVLOAD
_c201401311401
_dstaff
_y201401301200
_zstaff
040 _aMX-SnUAN
_bspa
_cMX-SnUAN
_erda
050 4 _aQA76.9.C643
100 1 _aGlesner, Manfred.
_eeditor.
_9301602
245 1 0 _aVLSI-SOC: From Systems to Chips :
_bIFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1–3, 2003, Darmstadt, Germany /
_cedited by Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney, Hans Eveking.
264 1 _aBoston, MA :
_bSpringer US,
_c2006.
300 _ax, 315 páginas,
_brecurso en línea.
336 _atexto
_btxt
_2rdacontent
337 _acomputadora
_bc
_2rdamedia
338 _arecurso en línea
_bcr
_2rdacarrier
347 _aarchivo de texto
_bPDF
_2rda
490 0 _aIFIP International Federation for Information Processing,
_x1571-5736 ;
_v200
500 _aSpringer eBooks
505 0 _aEffect of Power Optimizations on Soft Error Rate -- Dynamic Models for Substrate Coupling in Mixed-Mode Systems -- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs -- Automated Conversion of SystemC Fixed-Point Data Types -- Exploration of Sequential Depth by Evolutionary Algorithms -- Validation of Asynchronous Circuit Specifications Using IF/CADP -- On-Chip Property Verification Using Assertion Processors -- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems -- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications -- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans -- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures -- Optimizing SOC Test Resources Using Dual Sequences -- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits -- Low Power Java Processor for Embedded Applications -- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes -- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates -- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath -- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths -- Stuck-At-Fault Testability of SPP Three-Level Logic Forms.
520 _aInternational Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springeronline.com. For more information about IFIP, please visit www.ifip.org.
590 _aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700 1 _aReis, Ricardo.
_eeditor.
_9300500
700 1 _aIndrusiak, Leandro.
_eeditor.
_9301603
700 1 _aMooney, Vincent.
_eeditor.
_9301604
700 1 _aEveking, Hans.
_eeditor.
_9301605
710 2 _aSpringerLink (Servicio en línea)
_9299170
776 0 8 _iEdición impresa:
_z9780387334028
856 4 0 _uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/0-387-33403-3
_zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
942 _c14
999 _c278183
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