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008			150903s2005 xxu| o |||| 0|eng d
020			_a9780387254548 _9978-0-387-25454-8
024	7		_a10.1007/b107399 _2doi
035			_avtls000330151
039		9	_a201509031111 _bVLOAD _c201405070500 _dVLOAD _c201401311331 _dstaff _c201401311155 _dstaff _y201401291448 _zstaff _wmsplit0.mrc _x571
050		4	_aTK7888.4
100	1		_aEbendt, Rüdiger. _eautor _9302299
245	1	0	_aAdvanced BDD Optimization / _cby Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aX, 222 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aPreface. 1. Introduction. 2. Preliminaries. 2.1. Notation. 2.2. Boolean Functions. 2.3. Decomposition of Boolean Functions. 2.4. Reduced Ordered Binary Decision Diagrams -- 3. Exact node Minimization. 3.1. Branch and Bound Algorithm. 3.2. A*-Based Optimization. 3.3. Summary -- 4. Heuristic node Minimization. 4.1. Efficient Dynamic Minimization. 4.2. Improved Lower Bounds for Dynamic Reordering. 4.3. Efficient Forms of Improved Lower Bounds. 4.4. Combination of Improved Lower Bounds with Classical Bounds. 4.5. Experimental Results. 4.6. Summary -- 5. Path Minimization. 5.1. Minimization of Number of Paths. 5.2. Minimization of Expected Path Length. 5.3. Minimization of Average Path Length. 5.4. Summary -- 6. Relation between SAT and BDDS. 6.1. Davis-Putnam Procedure. 6.2. On the Relation between DP Procedure and BDDs. 6.3. Dynamic Variable Ordering Strategy for DP Procedure. 6.4. Experimental Results. 6.5. Summary -- 7. Final Remarks. References. Index.
520			_aThe size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore today’s design flow has to be improved to achieve a higher productivity. In Robustness and Usability in Modern Design Flows the current design methodology and verification methodology are analyzed, a number of deficiencies are identified and solutions suggested. Improvements in the methodology as well as in the underlying algorithms are proposed. An in-depth presentation of preliminary concepts makes the book self-contained. Based on this foundation major design problems are targeted. In particular, a complete tool flow for Synthesis for Testability of SystemC descriptions is presented. The resulting circuits are completely testable and test pattern generation in polynomial time is possible. Verification issues are covered in even more detail. A whole new paradigm for formal design verification is suggested. This is based upon design understanding, the automatic generation of properties and powerful tool support for debugging failures. All these new techniques are empirically evaluated and experimental results are provided. As a result, an enhanced design flow is created that provides more automation (i.e. better usability) and reduces the probability of introducing conceptual errors (i.e. higher robustness).
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aFey, Görschwin. _eautor _9302300
700	1		_aDrechsler, Rolf. _eautor _9302301
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387254531
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/b107399 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c278582 _d278582