000			03424nam a22003495i 4500
001			278681
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008			150903s2006 xxu| o |||| 0|eng d
020			_a9780387270388 _9978-0-387-27038-8
024	7		_a10.1007/b138536 _2doi
035			_avtls000330330
039		9	_a201509031101 _bVLOAD _c201405070512 _dVLOAD _c201401311337 _dstaff _c201401311201 _dstaff _y201401291452 _zstaff _wmsplit0.mrc _x750
050		4	_aTK7888.4
100	1		_aSpear, Chris. _eautor _9302465
245	1	0	_aSystemverilog for Verification : _bA Guide to Learning the Testbench Language Features / _cby Chris Spear.
264		1	_aBoston, MA : _bSpringer US, _c2006.
300			_aXXXIV, 301 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aVerification Guidelines -- Data Types -- Procedural Statements and Routines -- Basic OOP -- Connecting the Testbench and Design -- Randomization -- Threads and Interprocess Communication -- Advanced OOP and Guidelines -- Functional Coverage -- Advanced Interfaces.
520			_aBecome a SystemVerilog Expert! You can verify complex designs thoroughly and quickly if you start with the right tools. This book teaches you the SystemVerilog constructs for verification with over 300 examples. Learn proven techniques so you can build testbenches that automatically generate stimulus to catch those bugs. The SystemVerilog language contains hundreds of new features. This book shows you how to use the important ones to get your job done. You will learn how to use techniques such as * Interfaces and clocking blocks * Object oriented programming * Constrained random stimulus * Functional coverage * Logical assertions "SystemVerilog for Verification is a MUST prerequisite book for anyone involved in the creation of SystemVerilog testbenches, as standalone or in a framework like Synopsys VMM. I consider this work as a golden reference as it gets into the inner use of the language and provides excellent insights into practical coding styles. This book fills a needed void in explaining, in a very readable manner and with lots of examples and visuals, the key elements and applications of thelanguage for a verification methodology that supports constrained-random testing in a transaction-based methodology." Ben Cohen, Author/Consultant/Trainer, abv-sva.org http://abv-sva.org/ Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog's verification constructs. Chris is the author of the widely used File I/O PLI package for Verilog. Testbenches get more complex. You need this book to keep up! *** Includes over 300 examples *** Plus a foreword by Phil Moorby, creator of the Verilog language.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387270364
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/b138536 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c278681 _d278681