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001			278761
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007			cr nn 008mamaa
008			150903s2006 xxu| o |||| 0|eng d
020			_a9780387261225 _9978-0-387-26122-5
024	7		_a10.1007/b136837 _2doi
035			_avtls000330249
039		9	_a201509030444 _bVLOAD _c201405070504 _dVLOAD _c201401311334 _dstaff _c201401311158 _dstaff _y201401291450 _zstaff _wmsplit0.mrc _x669
050		4	_aTK7888.4
100	1		_aU, Seng-Pan. _eautor _9302595
245	1	0	_aDesign of Very High-Frequency Multirate Switched-Capacitor Circuits : _bExtending the Boundaries of CMOS Analog Front-End Filtering / _cby Seng-Pan U, Rui Paulo Martins, José Epifânio Franca.
264		1	_aBoston, MA : _bSpringer US, _c2006.
300			_aXXXII, 227 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aThe International Series in Engineering and Computer Science, Analog Circuits and Signal Processing, _x0893-3405 ; _v867
500			_aSpringer eBooks
505	0		_aImproved Multirate Polyphase-Based Interpolation Structures -- Practical Multirate SC Circuit Design Considerations -- Gain- and Offset- Compensation for Multirate SC Circuits -- Design of a 108 MHz Multistage SC Video Interpolating Filter -- Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter -- Experimental Results -- Conclusions.
520			_aDesign of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aMartins, Rui Paulo. _eautor _9302596
700	1		_aFranca, José Epifânio. _eautor _9302597
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387261218
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/b136837 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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