000 03317nam a22003735i 4500
001 278777
003 MX-SnUAN
005 20160429153918.0
007 cr nn 008mamaa
008 150903s2006 xxu| o |||| 0|eng d
020 _a9780387281339
_9978-0-387-28133-9
024 7 _a10.1007/0387281339
_2doi
035 _avtls000330499
039 9 _a201509030722
_bVLOAD
_c201404120454
_dVLOAD
_c201404090236
_dVLOAD
_c201401311343
_dstaff
_y201401291456
_zstaff
_wmsplit0.mrc
_x919
050 4 _aTK7888.4
100 1 _aNarendra, Siva G.
_eautor
_9302629
245 1 0 _aLeakage in Nanometer CMOS Technologies /
_cby Siva G. Narendra, Anantha Chandrakasan.
264 1 _aBoston, MA :
_bSpringer US,
_c2006.
300 _aX, 307 páginas,
_brecurso en línea.
336 _atexto
_btxt
_2rdacontent
337 _acomputadora
_bc
_2rdamedia
338 _arecurso en línea
_bcr
_2rdacarrier
347 _aarchivo de texto
_bPDF
_2rda
490 0 _aSeries on Integrated Circuits and Systems,
_x1558-9412
500 _aSpringer eBooks
505 0 _aTaxonomy of Leakage: Sources, Impact, and Solutions -- Leakage Dependence on Input Vector -- Power Gating and Dynamic Voltage Scaling -- Methodologies for Power Gating -- Body Biasing -- Process Variation and Adaptive Design -- Memory Leakage Reduction -- Active Leakage Reduction and Multi-Performance Devices -- Impact of Leakage Power and Variation on Testing -- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors -- Case Study: Leakage Reduction in the Intel Xscale Microprocessor -- Transistor Design to Reduce Leakage.
520 _aThe goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction. Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles. The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions. Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions. Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.
590 _aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700 1 _aChandrakasan, Anantha.
_eautor
_9302630
710 2 _aSpringerLink (Servicio en línea)
_9299170
776 0 8 _iEdición impresa:
_z9780387257372
856 4 0 _uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/0-387-28133-9
_zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999 _c278777
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