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001			278786
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008			150903s2005 xxu| o |||| 0|eng d
020			_a9780387239057 _9978-0-387-23905-7
024	7		_a10.1007/b103124 _2doi
035			_avtls000329995
039		9	_a201509030229 _bVLOAD _c201405070454 _dVLOAD _c201401311325 _dstaff _c201401311150 _dstaff _y201401291445 _zstaff _wmsplit0.mrc _x416
050		4	_aTK1-9971
100	1		_aQin, Zhanhai. _eautor _9302648
245	1	0	_aSymbolic Analysis and Reduction of VLSI Circuits / _cby Zhanhai Qin, Sheldon X. D. Tan, Chung-Kuan Cheng.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aXXII, 283 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aFundamentals -- Basics Of Circuit Analysis -- Linear VLSI Circuits -- Model-Order Reduction -- Generalized Y-? Transformation — Fundamental Theory -- Generalized Y-? Transformation — Advance Topics -- Y-? Transformation: Application I — Model Stabilization -- Y-? Transformation: Application II — Realizable Parasitic Reduction -- Analog VLSI Circuits -- Topological Analysis of Passive Networks -- Exact Symbolic Analysis Using Determinant Decision Diagrams -- S-Expanded Determinant Decision Diagrams for Symbolic Analysis -- DDD Based Approximation for Analog Behavioral Modeling -- Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction.
520			_aThe IC industry, including digital and analog circuit design houses, electrical design automation software vendors, library and IP providers, and foundries all face grand challenges in designing nanometer VLSI systems. The design productivity gap between nanometer VLSI technologies and today’s design capabilities mainly comes from the exponentially growing complexity of VLSI systems due to relentless pushing for integration. The physical effects on the performance and reliability of these systems are becoming more pronounced. Efficient modeling and reduction of both the passive and active circuits is essential for hierarchical and IP-based reuse design paradigms. Symbolic Analysis and Reducation of VLSI Circuits presents the symbolic approach to the modeling and reduction of both the passive parasitic linear networks and active analog circuits. It reviews classic symbolic analysis methods and presents state-of-art developments for interconnect reduction and the behavioral modeling of active analog circuits. The text includes the most updated discoveries such as Y-Delta transformation and DDD-graph symbolic representation which allow analysis and modeling of much larger circuitry than ever before.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aTan, Sheldon X. D. _eautor _9302649
700	1		_aCheng, Chung-Kuan. _eautor _9302650
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387239040
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/b103124 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c278786 _d278786