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008			150903s2006 xxu| o |||| 0|eng d
020			_a9780387255569 _9978-0-387-25556-9
024	7		_a10.1007/b135575 _2doi
035			_avtls000330165
039		9	_a201509030233 _bVLOAD _c201405070502 _dVLOAD _c201401311331 _dstaff _c201401311156 _dstaff _y201401291449 _zstaff _wmsplit0.mrc _x585
050		4	_aTK7888.4
100	1		_aBergeron, Janick. _eautor _9301502
245	1	0	_aVerification Methodology Manual for SystemVerilog / _cby Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale.
264		1	_aBoston, MA : _bSpringer US, _c2006.
300			_aXVIII, 510 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aVerification Planning -- Assertions -- Testbench Infrastructure -- Stimulus and Response -- Coverage-Driven Verification -- Assertions for Formal Tools -- System-Level Verification -- Processor Integration Verification.
520			_aFunctional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies. Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform. Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers. Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems. This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aCerny, Eduard. _eautor _9302758
700	1		_aHunter, Alan. _eautor _9302759
700	1		_aNightingale, Andrew. _eautor _9302760
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387255385
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/b135575 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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