000			03684nam a22003855i 4500
001			279171
003			MX-SnUAN
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007			cr nn 008mamaa
008			150903s2008 xxu| o |||| 0|eng d
020			_a9780387764740 _99780387764740
024	7		_a10.1007/9780387764740 _2doi
035			_avtls000332676
039		9	_a201509030235 _bVLOAD _c201404122223 _dVLOAD _c201404091954 _dVLOAD _y201402041035 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
100	1		_aPatra, Priyardarsan. _eautor _9303352
245	1	0	_aLow-Power High-Level Synthesis for Nanoscale CMOS Circuits / _cby Priyardarsan Patra, Elias Kougianos, Nagarajan Ranganathan, Saraju P. Mohanty.
264		1	_aBoston, MA : _bSpringer US, _c2008.
300			_brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aHigh-Level Synthesis Fundamentals -- Power Modeling and Estimation at Transistor and Logic Gate Levels -- Architectural Power Modeling and Estimation -- Power Reduction Fundamentals -- Energy or Average Power Reduction -- Peak Power Reduction -- Transient Power Reduction -- Leakage Power Reduction -- Conclusions and Future Direction.
520			_aLow-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation. The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals • Energy or Average Power Reduction • Peak Power Reduction • Transient Power Reduction • Leakage Power Reduction Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aKougianos, Elias. _eautor _9303353
700	1		_aRanganathan, Nagarajan. _eautor _9303354
700	1		_aMohanty, Saraju P. _eautor _9303355
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387764733
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-0-387-76474-0 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c279171 _d279171