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008			150903s2008 xxu| o |||| 0|eng d
020			_a9780387765303 _99780387765303
024	7		_a10.1007/9780387765303 _2doi
035			_avtls000332693
039		9	_a201509030756 _bVLOAD _c201404122227 _dVLOAD _c201404091957 _dVLOAD _y201402041035 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aSpear, Chris. _eautor _9302465
245	1	0	_aSystem Verilog for Verification : _bA Guide to Learning the Testbench Language Features / _cby Chris Spear.
250			_aSecond Edition.
264		1	_aBoston, MA : _bSpringer US, _c2008.
300			_axxxvI, 429 páginas _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_a1. Verification Guidelines -- 1.1 The Verification Process -- 1.2 The Verification Methodology Manual -- 1.3 Basic Testbench Functionality -- 1.4 Directed Testing -- 1.5 Methodology Basics -- 1.6 Constrained-Random Stimulus -- 1.7 What Should You Randomize? -- 1.8 Functional Coverage -- 1.9 Testbench Components -- 1.10 Layered Testbench -- 1.11 Building a Layered Testbench -- 1.12 Simulation Environment Phases -- 1.13 Maximum Code Reuse -- 1.14 Testbench Performance -- 1.15 Conclusion -- 2. Data Types -- 2.1 Built-in Data Types -- 2.2 Fixed-Size Arrays -- 2.3 Dynamic Arrays -- 2.4 Queues -- 2.5 Associative Arrays -- 2.6 Linked Lists -- 2.7 Array Methods -- 2.8 Choosing a Storage Type -- 2.9 Creating New Types with typedef -- 2.10 Creating User-Defined Structures -- 2.11 Type conversion -- 2.12 Enumerated Types -- 2.13 Constants -- 2.14 Strings -- 2.15 Expression Width -- 2.16 Conclusion -- 3. Procedural Statements and Routines -- 3.1 Procedural Statements -- 3.2 Tasks, Functions, and Void Functions -- 3.3 Task and Function Overview -- 3.4 Routine Arguments -- 3.5 Returning from a Routine -- 3.6 Local Data Storage -- 3.7 Time Values -- 3.8 Conclusion -- 4. Connecting The Testbench and Design -- 4.1 Separating the Testbench and Design -- 4.2 The Interface Construct -- 4.3 Stimulus Timing -- 4.4 Interface Driving and Sampling -- 4.5 Connecting It All Together -- 4.6 Top-Level Scope -- 4.7 Program — Module Interactions -- 4.8 SystemVerilog Assertions -- 4.9 The Four-Port ATM Router -- 4.10 The ref Port Direction -- 4.11 The End of Simulation -- 4.12 Directed Test for the LC3 Fetch Block -- 4.13 Conclusion -- 5. Basic Oop -- 5.1 Introduction -- 5.2 Think of Nouns, not Verbs -- 5.3 Your First Class -- 5.4 Where to Define a Class -- 5.5 OOP Terminology -- 5.6 Creating New Objects -- 5.7 Object Deallocation -- 5.8 Using Objects -- 5.9 Static Variables vs. Global Variables -- 5.10 Class Methods -- 5.11 Defining Methods Outside of the Class -- 5.12 Scoping Rules -- 5.13 Using One Class Inside Another -- 5.14 Understanding Dynamic Objects -- 5.15 Copying Objects -- 5.16 Public vs. Local -- 5.17 Straying Off Course -- 5.18 Building a Testbench -- 5.19 Conclusion -- 6. Randomization -- 6.1 Introduction -- 6.2 What to Randomize -- 6.3 Randomization in SystemVerilog -- 6.4 Constraint Details -- 6.5 Solution Probabilities -- 6.6 Controlling Multiple Constraint Blocks -- 6.7 Valid Constraints -- 6.8 In-line Constraints -- 6.9 The pre_randomize and post_randomize Functions -- 6.10 Random Number Functions -- 6.11 Constraints Tips and Techniques -- 6.12 Common Randomization Problems -- 6.13 Iterative and Array Constraints -- 6.14 Atomic Stimulus Generation vs. Scenario Generation -- 6.15 Random Control -- 6.16 Random Number Generators -- 6.17 Random Device Configuration -- 6.18 Conclusion -- 7. Threads and Interprocess Communication -- 7.1 Working with Threads -- 7.2 Disabling Threads -- 7.3 Interprocess Communication -- 7.4 Events -- 7.5 Semaphores -- 7.6 Mailboxes -- 7. -- 7.7 Building a Testbench with Threads and IPC -- 7.8 Conclusion -- 8. Advanced Oop and Testbench Guidelines -- 8.1 Introduction to Inheritance -- 8.2 Blueprint Pattern -- 8.3 Downcasting and Virtual Methods -- 8.4 Composition, Inheritance, and Alternatives -- 8.5 Copying an Object -- 8.6 Abstract Classes and Pure Virtual Methods -- 8.7 Callbacks -- 8.8 Parameterized Classes -- 8.9 Conclusion -- 9. Functional Coverage -- 9.1 Coverage Types -- 9.2 Functional Coverage Strategies -- 9.3 Simple Functional Coverage Example -- 9.4 Anatomy of a Cover Group -- 9.5 Triggering a Cover Group -- 9.6 Data Sampling -- 9.7 Cross Coverage -- 9.8 Generic Cover Groups -- 9.9 Coverage Options -- 9.10 Analyzing Coverage Data -- 9.11 Measuring Coverage Statistics During Simulation -- 9.12 Conclusion -- 10. Advanced Interfaces -- 10.1 Virtual Interfaces with the ATM Router -- 10.2 Connecting to Multiple Design Configurations -- 10.3 Procedural Code in an Interface -- 10.4 Conclusion -- 11. A Complete Systemverilog Testbench -- 11.1 Design Blocks -- 11.2 Testbench Blocks -- 11.3 Alternate Tests -- 11.4 Conclusion -- 12. Interfacing With C -- 12.1 Passing Simple Values -- 12.2 Connecting to a Simple C Routine -- 12.3 Connecting to C++ -- 12.4 Simple Array Sharing -- 12.5 Open arrays -- 12.6 Sharing Composite Types -- 12.7 Pure and Context Imported Methods -- 12.8 Communicating from C to System Verilog -- 12.9 Connecting Other Languages -- 12.10 Conclusion -- References.
520			_aNew! Expanded! Updated! Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include: The revision of nearly every explanation and code sample The inclusion of new chapters: "A Complete SystemVerilog Testbench" with a complete constrained random testbench for an ATM switch and "Interfacing with C" on the DPI (Directed Programming Interface) The addition of 70 new examples including larger ones such as a directed testbench at the end of chapter four An expanded index with 50% more entries and cross references "As digital integrated circuits relentlessly march towards a billion transistors and beyond, Verilog testbenches are running out of steam. With logic verification taking more effort than design, moving to a higher level of abstraction is the only choice. SystemVerilog appears to be the winner in the high-level verification language market and "SystemVerilog for Verification" is the book that will take working professionals and students alike from basic Verilog to the sophisticated structures needed to verify large and complex designs." Ronald W. Mehler, Professor of Electrical and Computer Engineering, California State University Northridge "It can be difficult to improve upon a great book, but Chris has achieved that goal - the second edition of this book is even better than the first! The explanations of abstract verification constructs are more detailed, and many more comprehensive examples make it easier to see how to apply SystemVerilog in object-oriented verification. The new chapter on the SystemVerilog Direct Programming Interface (DPI) is a very valuable addition. This second edition is a must-have book for every engineer involved in Verilog and SystemVerilog design and verification. The book serves well both as a general SystemVerilog reference and for learning object-oriented verification techniques. This book is such an invaluable reference, that my company includes a copy as part of the student training materials with every SystemVerilog verification course we teach!" Stuart Sutherland, SystemVerilog Training Consultant, Sutherland HDL, Inc. Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog’s verification constructs. Testbenches are growing more complex. You need this book to keep up. Includes nearly 500 code samples and 70 figures.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781441945617
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-0-387-76530-3 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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