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008			150903s2007 xxu| o |||| 0|eng d
020			_a9780387485508 _99780387485508
024	7		_a10.1007/0387485503 _2doi
035			_avtls000331576
039		9	_a201509030721 _bVLOAD _c201404120630 _dVLOAD _c201404090410 _dVLOAD _c201401311420 _dstaff _y201401301213 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aSaxena, Prashant. _eautor _9304220
245	1	0	_aRouting Congestion in VLSI Circuits: Estimation and Optimization / _cby Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar.
264		1	_aBoston, MA : _bSpringer US, _c2007.
300			_axiv, 248 páginas, _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aSeries on Integrated Circuits and Systems, _x1558-9412
500			_aSpringer eBooks
505	0		_aThe Origins of Congestion -- An Introduction to Routing Congestion -- The Estimation of Congestion -- Placement-level Metrics for Routing Congestion -- Synthesis-level Metrics for Routing Congestion -- The Optimization of Congestion -- Congestion Optimization During Interconnect Synthesis and Routing -- Congestion Optimization During Placement -- Congestion Optimization During Technology Mapping and Logic Synthesis -- Congestion Implications of High Level Design.
520			_aWith the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware. Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design. Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aShelar, Rupesh S. _eautor _9304221
700	1		_aSapatnekar, Sachin S. _eautor _9304222
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387300375
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/0-387-48550-3 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c279732 _d279732