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001			280561
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007			cr nn 008mamaa
008			150903s2009 xxu| o |||| 0|eng d
020			_a9780387938202 _99780387938202
024	7		_a10.1007/9780387938202 _2doi
035			_avtls000333391
039		9	_a201509030203 _bVLOAD _c201404130429 _dVLOAD _c201404092218 _dVLOAD _y201402041110 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
100	1		_aChadha, Rakesh. _eautor _9305570
245	1	0	_aStatic Timing Analysis for Nanometer Designs : _bA Practical Approach / _cby Rakesh Chadha, J. Bhasker.
264		1	_aBoston, MA : _bSpringer US, _c2009.
300			_brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aSTA Concepts -- Standard Cell Library -- Interconnect Parasitics -- Delay Calculation -- Crosstalk and Noise -- Configuring the STA Environment -- Timing Verification -- Interface Analysis -- Robust Verification.
520			_aStatic Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aBhasker, J. _eautor _9305571
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9780387938196
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-0-387-93820-2 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c280561 _d280561