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008			150903s2007 ne | o |||| 0|eng d
020			_a9781402050817 _99781402050817
024	7		_a10.1007/140205081-X _2doi
035			_avtls000335033
039		9	_a201509030250 _bVLOAD _c201404120915 _dVLOAD _c201404090653 _dVLOAD _y201402041249 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aHenzler, Stephan. _eautor _9308256
245	1	0	_aPower Management of Digital Circuits in Deep Sub-Micron CMOS Technologies / _cby Stephan Henzler.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_axvI, 183 páginas 127 ilustraciones _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aAdvanced Microelectronics, _x1437-0387 ; _v25
500			_aSpringer eBooks
505	0		_aTO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN -- LOGIC WITH MULTIPLE SUPPLY VOLTAGES -- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES -- FORCING OF TRANSISTOR STACKS -- POWER GATING -- CONCLUSION.
520			_aIn the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402050800
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/1-4020-5081-X _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c282005 _d282005