000			03431nam a22003855i 4500
001			282007
003			MX-SnUAN
005			20160429154129.0
007			cr nn 008mamaa
008			150903s2007 ne | o |||| 0|eng d
020			_a9781402051883 _99781402051883
024	7		_a10.1007/9781402051883 _2doi
035			_avtls000335076
039		9	_a201509030806 _bVLOAD _c201404300257 _dVLOAD _y201402041250 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aChiang, Charles C. _eautor _9308258
245	1	0	_aDesign for Manufacturability and Yield for Nano-Scale CMOS / _cby Charles C. Chiang, Jamil Kawa.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aSeries on Integrated Circuits and Systems, _x1558-9412
500			_aSpringer eBooks
505	0		_aRandom Defects -- Systematic Yield - Lithography -- Systematic Yield - Chemical Mechanical Polishing (CMP) -- Variability & Parametric Yield -- Design for Yield -- Yield Prediction -- Conclusions.
520			_aAs we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility. Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aKawa, Jamil. _eautor _9308259
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402051876
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4020-5188-3 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
942			_c14
999			_c282007 _d282007