000			03257nam a22003855i 4500
001			282704
003			MX-SnUAN
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007			cr nn 008mamaa
008			150903s2006 ne | o |||| 0|eng d
020			_a9781402048265 _99781402048265
024	7		_a10.1007/1402048262 _2doi
035			_avtls000334926
039		9	_a201509030225 _bVLOAD _c201404120904 _dVLOAD _c201404090643 _dVLOAD _y201402041246 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aKogel, Tim. _eautor _9309656
245	1	0	_aIntegrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms / _cby Tim Kogel, Rainer Leupers, Heinrich Meyr.
264		1	_aDordrecht : _bSpringer Netherlands, _c2006.
300			_axiv, 199 páginas _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aForeword. Preface -- 1. Introduction -- 2. Embedded SOC Applications -- 3. Classification of Platform Elements -- 4. System Level Design Principles -- 5. Related Work -- 6. Methodology Overview -- 7. Unified Timing Model -- 8. MP-SOC Simulation Framework -- 9. Case Study -- 10. Summary -- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework -- List of Figures. List of Tables. References -- Index.
520			_aThe drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification. In response to the vast complexity of heterogeneous multi-processor platforms the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models. Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aLeupers, Rainer. _eautor _9308697
700	1		_aMeyr, Heinrich. _eautor _9308696
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402048258
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/1-4020-4826-2 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c282704 _d282704