000			03288nam a22003735i 4500
001			282767
003			MX-SnUAN
005			20160429154205.0
007			cr nn 008mamaa
008			150903s2007 ne | o |||| 0|eng d
020			_a9781402055461 _99781402055461
024	7		_a10.1007/9781402055461 _2doi
035			_avtls000335228
039		9	_a201509030236 _bVLOAD _c201404300258 _dVLOAD _y201402041254 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aNedjah, Nadia. _eautor _9309754
245	1	0	_aCo-design for System Acceleration : _bA Quantitative Approach / _cby Nadia Nedjah, Luiza De Macedo Mourelle.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_axIx, 229 páginas _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aThe Co-design Methodology -- The Co-design System -- VHDL Model of the Co-design System -- Shared Memory Configuration -- Dual-port Memory Configuration -- Cache Memory Configuration -- Advanced Topics and Further Research.
520			_aIn Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aMourelle, Luiza De Macedo. _eautor _9309755
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402055454
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4020-5546-1 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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