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008			150903s2008 ne | o |||| 0|eng d
020			_a9781402085888 _99781402085888
024	7		_a10.1007/9781402085888 _2doi
035			_avtls000336062
039		9	_a201509030818 _bVLOAD _c201404300311 _dVLOAD _y201402041339 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aCoussy, Philippe. _eeditor. _9309841
245	1	0	_aHigh-Level Synthesis : _bFrom Algorithm to Digital Circuit / _cedited by Philippe Coussy, Adam Morawiec.
264		1	_aDordrecht : _bSpringer Netherlands, _c2008.
300			_brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aUser Needs -- High-Level Synthesis: A Retrospective -- Catapult Synthesis: A Practical Introduction to Interactive C Synthesis -- Algorithmic Synthesis Using PICO -- High-Level SystemC Synthesis with Forte's Cynthesizer -- AutoPilot: A Platform-Based ESL Synthesis System -- “All-in-C” Behavioral Synthesis and Verification with CyberWorkBench -- Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions -- GAUT: A High-Level Synthesis Tool for DSP Applications -- User Guided High Level Synthesis -- Synthesis of DSP Algorithms from Infinite Precision Specifications -- High-Level Synthesis of Loops Using the Polyhedral Model -- Operation Scheduling: Algorithms and Applications -- Exploiting Bit-Level Design Techniques in Behavioural Synthesis -- High-Level Synthesis Algorithms for Power and Temperature Minimization.
520			_aThe successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools and approaches are required. The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse. This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. High-Level Synthesis: from Algorithm to Digital Circuit should be on each designer’s and CAD developer’s shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aMorawiec, Adam. _eeditor. _9308953
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402085871
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4020-8588-8 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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