000			03618nam a22003855i 4500
001			283054
003			MX-SnUAN
005			20160429154217.0
007			cr nn 008mamaa
008			150903s2008 ne | o |||| 0|eng d
020			_a9781402083013 _99781402083013
024	7		_a10.1007/9781402083013 _2doi
035			_avtls000335936
039		9	_a201509030255 _bVLOAD _c201404300309 _dVLOAD _y201402041336 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aSemenov, Oleg. _eautor _9310282
245	1	0	_aESD Protection Device and Circuit Design for Advanced CMOS Technologies / _cby Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev.
264		1	_aDordrecht : _bSpringer Netherlands, _c2008.
300			_brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aESD Models and Test Methods -- ESD Devices for Input/Output Protection -- Circuit Design Concepts for ESD Protection -- ESD Power Clamps -- ESD Protection Circuits for High-Speed I/OS -- ESD Protection for Smart Power Applications -- ESD Protection for RF Circuits -- Conclusion.
520			_aThe challenges associated with the design and implementation of Electrostatic Discharge (ESD) protection circuits are becoming increasingly complex as technology is scaled well into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There are several challenges that must be met in order to design robust ESD circuits today. Due to technology scaling and proliferation of automated handling, ESD failures in ICs caused by Charged Device Model (CDM) are increasing. CDM discharges can cause latent damages which could degrade and eventually lead to definite failures in the ICs. The ESD protection design for current and future sub-65nm CMOS circuits is a challenge for high I/O count, multiple power domains and flip-chip products. ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results demonstrates its strengths.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aSarbishaei, Hossein. _eautor _9310283
700	1		_aSachdev, Manoj. _eautor _9299706
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402083006
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4020-8301-3 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c283054 _d283054