000			03211nam a22003855i 4500
001			283508
003			MX-SnUAN
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007			cr nn 008mamaa
008			150903s2008 ne | o |||| 0|eng d
020			_a9781402083631 _99781402083631
024	7		_a10.1007/9781402083631 _2doi
035			_avtls000335962
039		9	_a201509030817 _bVLOAD _c201404300309 _dVLOAD _y201402041337 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aPavlov, Andrei. _eautor _9311063
245	1	0	_aCMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : _bProcess-Aware SRAM Design and Test / _cby Andrei Pavlov, Manoj Sachdev.
264		1	_aDordrecht : _bSpringer Netherlands, _c2008.
300			_brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aFrontiers In Electronic Testing, _x0929-1296 ; _v40
500			_aSpringer eBooks
505	0		_aand Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.
520			_aAs technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aSachdev, Manoj. _eautor _9299706
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781402083624
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4020-8363-1 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c283508 _d283508