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001			285040
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008			150903s2011 xxu| o |||| 0|eng d
020			_a9781441968654 _99781441968654
024	7		_a10.1007/9781441968654 _2doi
035			_avtls000338782
039		9	_a201509030310 _bVLOAD _c201404300350 _dVLOAD _y201402060918 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aHansson, Andreas. _eautor _9313115
245	1	0	_aOn-Chip Interconnect with aelite : _bComposable and Predictable Systems / _cby Andreas Hansson, Kees Goossens.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2011.
300			_ax, 210 páginas _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aEmbedded Systems, _x2193-0155
500			_aSpringer eBooks
520			_aOn-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aGoossens, Kees. _eautor _9313116
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781441964960
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4419-6865-4 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c285040 _d285040