000			03065nam a22003735i 4500
001			285545
003			MX-SnUAN
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007			cr nn 008mamaa
008			150903s2010 xxu| o |||| 0|eng d
020			_a9781441964816 _99781441964816
024	7		_a10.1007/9781441964816 _2doi
035			_avtls000338678
039		9	_a201509030326 _bVLOAD _c201404300349 _dVLOAD _y201402060916 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aSingh, Gaurav. _eautor _9313793
245	1	0	_aLow Power Hardware Synthesis from Concurrent Action-Oriented Specifications / _cby Gaurav Singh, Sandeep K. Shukla.
264		1	_aNew York, NY : _bSpringer New York, _c2010.
300			_ax, 240 páginas 200 ilustraciones, 100 ilustraciones en color. _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aRelated Work -- Background -- Low-Power Problem Formalization -- Heuristics for Power Savings -- Complexity Analysis of Scheduling in CAOS-Based Synthesis -- Dynamic Power Optimizations -- Peak Power Optimizations -- Verifying Peak Power Optimizations Using SPIN Model Checker -- Epilogue.
520			_aLow Power Hardware Synthesis from Concurrent Action-Oriented Specifications Gaurav Singh Sandeep K. Shukla This book introduces novel techniques for generating low-power hardware from a high-level description of a design in terms of Concurrent Action-Oriented Specifications (CAOS). It also describes novel techniques for formal verification of such designs. It will provide the readers with definitions of various power optimization and formal verification problems related to CAOS-based synthesis, necessary background concepts, techniques to generate hardware according to the design’s power requirements, and detailed experimental results obtained by applying the techniques introduced on realistic hardware designs. •Presents detailed analysis of various power optimization problems associated with high-level synthesis, as well as novel techniques for reducing power consumption of hardware designs at a higher level of abstraction; •Discusses various formal verification issues associated with synthesizing different possible versions of a hardware design (differing in their latency, area, and/or power consumption); •Includes detailed experimental results obtained by applying the techniques introduced on benchmark hardware designs.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aShukla, Sandeep K. _eautor _9309934
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781441964809
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4419-6481-6 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c285545 _d285545