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001			285734
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008			150903s2010 xxu| o |||| 0|eng d
020			_a9781441909596 _99781441909596
024	7		_a10.1007/9781441909596 _2doi
035			_avtls000338151
039		9	_a201509030322 _bVLOAD _c201404300341 _dVLOAD _y201402060903 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aLin, Youn-Long Steve. _eautor _9308685
245	1	0	_aVLSI Design for Video Coding : _bH.264/AVC Encoding from Standard Specification to Chip / _cby Youn-Long Steve Lin, Chao-Yang Kao, Hung-Chih Kuo, Jian-Wen Chen.
250			_a1st.
264		1	_aBoston, MA : _bSpringer US, _c2010.
300			_axI, 176 páginas 308 ilustraciones, 154 ilustraciones en color. _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_ato Video Coding and H.264/AVC -- Intra Prediction -- Integer Motion Estimation -- Fractional Motion Estimation -- Motion Compensation -- Transform Coding -- Deblocking Filter -- CABAC Encoder -- System Integration.
520			_aBack Cover Copy VLSI Design for Video Coding By: Youn-Long Lin Chao-Yang Kao Jian-Wen Chen Hung-Chih Kuo High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing. This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding. • Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding; • Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA; • Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aKao, Chao-Yang. _eautor _9314069
700	1		_aKuo, Hung-Chih. _eautor _9314070
700	1		_aChen, Jian-Wen. _eautor _9314071
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781441909589
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4419-0959-6 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c285734 _d285734