000			02816nam a22003855i 4500
001			286898
003			MX-SnUAN
005			20160429154521.0
007			cr nn 008mamaa
008			150903s2013 xxu| o |||| 0|eng d
020			_a9781461408185 _99781461408185
024	7		_a10.1007/9781461408185 _2doi
035			_avtls000340410
039		9	_a201509030348 _bVLOAD _c201404300415 _dVLOAD _y201402061024 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aTK7888.4
100	1		_aSingh, Jawar. _eautor _9315830
245	1	0	_aRobust SRAM Designs and Analysis / _cby Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2013.
300			_axI, 166 páginas 167 ilustraciones _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
500			_aSpringer eBooks
505	0		_aIntroduction to SRAM -- Design Metrics of SRAM Bitcell -- Single-ended SRAM Bitcell Design -- 2-Port SRAM Bitcell Design -- SRAM Bitcell Design Using Unidirectional Devices -- NBTI and its Effect on SRAM.
520			_aThis book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aMohanty, Saraju P. _eautor _9303355
700	1		_aPradhan, Dhiraj K. _eautor _9315831
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9781461408178
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-1-4614-0818-5 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c286898 _d286898