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008 150903s2005 xxk| o |||| 0|eng d
020 _a9781846281457
_99781846281457
024 7 _a10.1007/1846281458
_2doi
035 _avtls000343688
039 9 _a201509030252
_bVLOAD
_c201404120948
_dVLOAD
_c201404090726
_dVLOAD
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_zstaff
040 _aMX-SnUAN
_bspa
_cMX-SnUAN
_erda
050 4 _aTK7888.4
100 1 _aSonza Reorda, Matteo.
_eeditor.
_9322753
245 1 0 _aSystem-level Test and Validation of Hardware/Software Systems /
_cedited by Matteo Sonza Reorda, Zebo Peng, Massimo Violante.
264 1 _aLondon :
_bSpringer London,
_c2005.
300 _axii, 179 páginas
_brecurso en línea.
336 _atexto
_btxt
_2rdacontent
337 _acomputadora
_bc
_2rdamedia
338 _arecurso en línea
_bcr
_2rdacarrier
347 _aarchivo de texto
_bPDF
_2rda
490 0 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v17
500 _aSpringer eBooks
505 0 _aModeling Permanent Faults -- Test Generation: A Symbolic Approach -- Test Generation: A Heuristic Approach -- Test Generation: A Hierarchical Approach -- Test Program Generation from High-level Microprocessor Descriptions -- Tackling Concurrency and Timing Problems -- An Approach to System-level Design for Test -- System-level Dependability Analysis.
520 _aNew manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue. System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: • modeling of bugs and defects; • stimulus generation for validation and test purposes (including timing errors; • design for testability. For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.
590 _aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700 1 _aPeng, Zebo.
_eeditor.
_9309329
700 1 _aViolante, Massimo.
_eeditor.
_9301512
710 2 _aSpringerLink (Servicio en línea)
_9299170
776 0 8 _iEdición impresa:
_z9781852338992
856 4 0 _uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/1-84628-145-8
_zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999 _c291454
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