000			04550nam a22003855i 4500
001			295140
003			MX-SnUAN
005			20160429155216.0
007			cr nn 008mamaa
008			150903s2005 gw | o |||| 0|eng d
020			_a9783540319405 _99783540319405
024	7		_a10.1007/11545262 _2doi
035			_avtls000348057
039		9	_a201509030738 _bVLOAD _c201404121033 _dVLOAD _c201404090810 _dVLOAD _y201402071018 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aQA76.9.A25
100	1		_aRao, Josyula R. _eeditor. _9329337
245	1	0	_aCryptographic Hardware and Embedded Systems – CHES 2005 : _b7th International Workshop, Edinburgh, UK, August 29 – September 1, 2005. Proceedings / _cedited by Josyula R. Rao, Berk Sunar.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2005.
300			_axiv, 458 páginas Also available online. _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aLecture Notes in Computer Science, _x0302-9743 ; _v3659
500			_aSpringer eBooks
505	0		_aSide Channels I -- Resistance of Randomized Projective Coordinates Against Power Analysis -- Templates as Master Keys -- A Stochastic Model for Differential Side Channel Cryptanalysis -- Arithmetic for Cryptanalysis -- A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis -- Further Hidden Markov Model Cryptanalysis -- Low Resources -- Energy-Efficient Software Implementation of Long Integer Modular Arithmetic -- Short Memory Scalar Multiplication on Koblitz Curves -- Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 ?P -- Special Purpose Hardware -- SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers -- Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization -- Design of Testable Random Bit Generators -- Hardware Attacks and Countermeasures I -- Successfully Attacking Masked AES Hardware Implementations -- Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints -- Masking at Gate Level in the Presence of Glitches -- Arithmetic for Cryptography -- Bipartite Modular Multiplication -- Fast Truncated Multiplication for Cryptographic Applications -- Using an RSA Accelerator for Modular Inversion -- Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings -- Side Channel II (EM) -- EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA -- Security Limits for Compromising Emanations -- Security Evaluation Against Electromagnetic Analysis at Design Time -- Side Channel III -- On Second-Order Differential Power Analysis -- Improved Higher-Order Side-Channel Attacks with FPGA Experiments -- Trusted Computing -- Secure Data Management in Trusted Computing -- Hardware Attacks and Countermeasures II -- Data Remanence in Flash Memory Devices -- Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment -- Hardware Attacks and Countermeasures III -- DPA Leakage Models for CMOS Logic Circuits -- The “Backend Duplication” Method -- Efficient Hardware I -- Hardware Acceleration of the Tate Pairing in Characteristic Three -- Efficient Hardware for the Tate Pairing Calculation in Characteristic Three -- Efficient Hardware II -- AES on FPGA from the Fastest to the Smallest -- A Very Compact S-Box for AES.
520			_aThis book constitutes the refereed proceedings of the 7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005, held in Edinburgh, UK in August/September 2005. The 32 revised full papers presented were carefully reviewed and selected from 108 submissions. The papers are organized in topical sections on side channels, arithmetic for cryptanalysis, low resources, special purpose hardware, hardware attacks and countermeasures, arithmetic for cryptography, trusted computing, and efficient hardware.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aSunar, Berk. _eeditor. _9299219
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9783540284741
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/11545262 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c295140 _d295140