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007			cr nn 008mamaa
008			150903s2007 gw | o |||| 0|eng d
020			_a9783540736257 _99783540736257
024	7		_a10.1007/9783540736257 _2doi
035			_avtls000350641
039		9	_a201509030459 _bVLOAD _c201405060238 _dVLOAD _y201402171102 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aQA75.5-76.95
100	1		_aVassiliadis, Stamatis. _eeditor. _9310780
245	1	0	_aEmbedded Computer Systems: Architectures, Modeling, and Simulation : _b7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007. Proceedings / _cedited by Stamatis Vassiliadis, Mladen Berekovi?, Timo D. Hämäläinen.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2007.
300			_axvii, 466 páginas _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aLecture Notes in Computer Science, _x0302-9743 ; _v4599
500			_aSpringer eBooks
505	0		_aKeynotes -- Software Is the Answer But What Is the Question? -- Integrating VLIW Processors with a Network on Chip -- System Modeling and Simulation -- Communication Architecture Simulation on the Virtual Synchronization Framework -- A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems -- Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration -- SC2SCFL: Automated SystemC to Translation -- VLSI Architectures -- Model and Validation of Block Cleaning Cost for Flash Memory -- VLSI Architecture for MRF Based Stereo Matching -- Low-Power Twiddle Factor Unit for FFT Computation -- Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors -- Scheduling & Programming Models -- An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code -- Improving TriMedia Cache Performance by Profile Guided Code Reordering -- A Streaming Machine Description and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing -- Strategies for Compiling ?TC to Novel Chip Multiprocessors -- Image Quantisation on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System -- Reconfigurable Architectures -- MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing -- FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder -- Evaluating Large System-on-Chip on Multi-FPGA Platform -- Design Space Exploration -- Efficiency Measures for Multimedia SOCs -- On-Chip Bus Modeling for Power and Performance Estimation -- A Framework Introducing Model Reversibility in SoC Design Space Exploration -- Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration -- Processor Components -- Resource Conflict Detection in Simulation of Function Unit Pipelines -- A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing -- High-Bandwidth Address Generation Unit -- An IP Core for Embedded Java Systems -- Embedded Processors -- Parallel Memory Architecture for TTA Processor -- A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size -- Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction -- A Study of Energy Saving in Customizable Processors -- SoC for SDR -- Trends in Low Power Handset Software Defined Radio -- Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals -- Area Efficient Fully Programmable Baseband Processors -- The Next Generation Challenge for Software Defined Radio -- Design Methodology for Software Radio Systems -- Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC -- A Comparative Study of Different FFT Architectures for Software Defined Radio -- Wireless Sensors -- Design of 100 ?W Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring -- Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network -- System Architecture Modeling of an UWB Receiver for Wireless Sensor Network -- An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks -- SensorOS: A New Operating System for Time Critical WSN Applications -- Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks -- k ?+? Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks.
520			_aThis book constitutes the refereed proceedings of the 7th International Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS 2007, held in Samos, Greece in July 2007. The 44 revised full papers presented together with 2 keynote talks were thoroughly reviewed and selected from 116 submissions. The papers are organized in topical sections on system modeling and simulation, VLSI architectures, scheduling and programming models, multi-processor architectures, reconfigurable architectures, design space exploration, processor components, embedded processors, SoC for SDR, and wireless sensors.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aBerekovi?, Mladen. _eeditor. _9332996
700	1		_aHämäläinen, Timo D. _eeditor. _9319001
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9783540736226
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-3-540-73625-7 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
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999			_c297311 _d297311