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007			cr nn 008mamaa
008			150903s2013 gw | o |||| 0|eng d
020			_a9783642450730 _99783642450730
024	7		_a10.1007/9783642450730 _2doi
035			_avtls000362323
039		9	_a201509031037 _bVLOAD _c201405070328 _dVLOAD _y201402211047 _zstaff
040			_aMX-SnUAN _bspa _cMX-SnUAN _erda
050		4	_aQA76.9.A73
100	1		_aBurg, Andreas. _eeditor. _9347866
245	1	0	_aVLSI-SoC: From Algorithms to Circuits and System-on-Chip Design : _b20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers / _cedited by Andreas Burg, Ay?e Co?kun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg : _bImprint: Springer, _c2013.
300			_ax, 235 páginas 121 ilustraciones _brecurso en línea.
336			_atexto _btxt _2rdacontent
337			_acomputadora _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_aarchivo de texto _bPDF _2rda
490	0		_aIFIP Advances in Information and Communication Technology, _x1868-4238 ; _v418
500			_aSpringer eBooks
505	0		_aFPGA-Based High-Speed Authenticated Encryption System -- A Smart Memory Accelerated Computed Tomography Parallel Backprojection -- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure -- Spatially-Varying Image Warping: Evaluations and VLSI Implementations -- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing -- Configurable Low-Latency Interconnect for Multi-core Clusters -- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks -- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections -- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture -- CMOS Implementation of Threshold Gates with Hysteresis -- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.
520			_aThis book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.
590			_aPara consulta fuera de la UANL se requiere clave de acceso remoto.
700	1		_aCo?kun, Ay?e. _eeditor. _9347867
700	1		_aGuthaus, Matthew. _eeditor. _9347868
700	1		_aKatkoori, Srinivas. _eeditor. _9347869
700	1		_aReis, Ricardo. _eeditor. _9300500
710	2		_aSpringerLink (Servicio en línea) _9299170
776	0	8	_iEdición impresa: _z9783642450723
856	4	0	_uhttp://remoto.dgb.uanl.mx/login?url=http://dx.doi.org/10.1007/978-3-642-45073-0 _zConectar a Springer E-Books (Para consulta externa se requiere previa autentificación en Biblioteca Digital UANL)
942			_c14
999			_c308068 _d308068